Field of the Invention: The present invention relates in general to memory array repair and, in particular, to devices and methods for repairing memory arrays, such as dynamic random access memory arrays, by storing each individual bit in multiple memory cells in the arrays.
State of the Art: In general, Dynamic Random Access Memory (DRAM) arrays store digital information in the form of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits by storing the bits as electric charges on capacitors. DRAM arrays then retrieve the stored bits by discharging their representative electric charges to a conductor, such as a digit line, and then detecting a change in voltage on the conductor resulting from the discharge. When any of the capacitors in a DRAM array are unable to store a sufficient electric charge to cause a detectable change in voltage on a conductor when discharged to the conductor, any xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d bits stored as electric charges on those capacitors cannot be retrieved by the array. In this circumstance, the array must be repaired by replacing the failing capacitors with redundant capacitors in redundant rows or columns in the array. If too many of the redundant capacitors also fail, then the array must be discarded.
More specifically, a conventional DRAM array 10 shown in FIG. 1 stores digital information in the form of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits by storing the bits as electric charges on storage capacitors 12, 14, and 16 in memory cells 18, 20, 22 and 24 arranged along word lines (i.e., rows) WL0, WL1, . . . , and WLm and complementary pairs of digit lines (i.e., columns) DO and DO*, D1 and D1*, ., and Dn and Dn*. Of course, while the DRAM array 10 is shown in FIG. 1 as having only nine memory cells in order to simplify description, the array 10 typically includes thousands or millions of memory cells.
The DRAM array 10 stores a xe2x80x9c1xe2x80x9d bit in the memory cell 18, for example, by energizing the word line WL0 to activate an NMOS transistor 26. The DRAM array 10 then applies a xe2x80x9c1xe2x80x9d bit voltage equal to a supply voltage VCC (e.g., 3.3 Volts) to the digit line D0, causing current to flow from the digit line D0, through the activated NMOS transistor 26 and the storage capacitor 12, and to a cell plate voltage DVC2 typically equal to one half the supply voltage VCC. As this current flows, the storage capacitor 12 stores positive electric charge received from the digit line D0, causing a voltage VS1, on the storage capacitor 12 to increase. When the voltage VS1 on the storage capacitor 12 equals the xe2x80x9c1xe2x80x9d bit voltage on the digit line D0, current stops flowing through the storage capacitor 12. A short time later, the DRAM array 10 de-energizes the word line WL0 to de-activate the NMOS transistor 26 and isolate the storage capacitor 12 from the digit line D0, thereby preventing the positive electric charge stored on the storage capacitor 12 from discharging back to the digit line D0.
Similarly, the DRAM array 10 stores a xe2x80x9c0xe2x80x9d bit in the memory cell 20, for example, by energizing the word line WL1 to activate an NMOS transistor 28. The DRAM array 10 then applies a xe2x80x9c0xe2x80x9d bit voltage approximately equal to a reference voltage VSS (e.g., 0.0 Volts) to the digit line D0, causing current to flow from the cell plate voltage DVC2, through the storage capacitor 14 and the activated NMOS transistor 28, and to the digit line D0. As this current flows, the storage capacitor 14 stores negative electric charge received from the digit line D0, causing a voltage VS2 on the storage capacitor 14 to decrease. When the voltage VS2 equals the xe2x80x9c0xe2x80x9d bit voltage on the digit line D0, current stops flowing through the storage capacitor 14. A short time later, the DRAM array 10 de-energizes the word line WL1 to deactivate the NMOS transistor 28 and isolate the storage capacitor 14 from the digit line D0, thereby preventing the negative electric charge stored on the storage capacitor 14 from discharging back to the digit line D0.
The DRAM array 10 stores xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits in the memory cells 22 arranged along the complementary digit lines D0*, D1*, . . . , and Dn* in a manner similar to that described above, with the exception that the xe2x80x9c1xe2x80x9d bit voltage for these cells is approximately equal to the reference voltage Vss and the xe2x80x9c0xe2x80x9d bit voltage equals the supply voltage VCC.
The DRAM array 10 retrieves xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits stored in the manner described above in the memory cells 18, 20, 22, and 24 by discharging electric charges stored on the storage capacitors 12, 14, and 16 to the digit lines D0, D0*, D1, D1*, . . . , Dn, and Dn* and then detecting a change in voltage on the digit lines D0, D0*, D1, D1*, . . . , Dn, and Dn* resulting from the discharge with sense amplifiers (0), (1), . . . , and (n).
For example, the DRAM array 10 retrieves the xe2x80x9c1xe2x80x9d bit stored in the memory cell 18 by first equilibrating the voltages on the digit lines D0 and D0* to the cell plate voltage DVC2. The DRAM array 10 then energizes the word line WL0 to activate the NMOS transistor 26, causing the positive electric charge stored on the storage capacitor 12 to discharge through the activated NMOS transistor 26 to the digit line D0. As the positive electric charge discharges, the voltage on the digit line D0 rises by an amount VSENSE calculated as follows:
VSENSE=(VS xe2x88x92DVC2)*CS/(CD+CS)
where VS is the voltage VS1 on the storage capacitor 12, CS is the capacitance of the storage capacitor 12, and CD is the capacitance of the digit line D0. When the rise in voltage VSENSE on the digit line D0 causes a difference in voltages between the digit lines D0 and D0* to exceed a detection threshold (typically about 150 mVolts) of the sense amplifier (0), the sense amplifier (0) responds by driving the voltage on the digit line D0 to the supply voltage VCC and by driving the voltage on the digit line D0* approximately to the reference voltage VSS. Input/output gating circuitry, DC sense amplifiers, and an output buffer (not shown) then transmit these voltages from the digit lines D0 and D0* to external circuitry as a xe2x80x9c1xe2x80x9d bit.
Likewise, the DRAM array 10 retrieves the xe2x80x9c0xe2x80x9d bit stored in the memory cell 20, for example, by first equilibrating the voltages on the digit lines D0 and D0* to the cell plate voltage DVC2. The DRAM array 10 then energizes the word line WL1 to activate the NMOS transistor 28, causing the negative electric charge stored on the storage capacitor 14 to discharge through the activated NMOS transistor 28 to the digit line D0. As the negative electric charge discharges, the voltage on the digit line D0 falls by an amount VSENSE, calculated as described above, where VS is the voltage VS2 on the storage capacitor 14 and CS is the capacitance of the storage capacitor 14. When the drop in voltage VSENSE on the digit line D0 causes the difference in voltages between the digit lines D0 and D0* to exceed the detection threshold of the sense amplifier (0), the sense amplifier (0) responds by driving the voltage on the digit line D0 approximately to the reference voltage VSS and by driving the voltage on the digit line D0* to the supply voltage VCC. The input/output gating circuitry, DC sense amplifiers, and output buffer then transmit these voltages from the digit lines D0 and D0* to external circuitry as a xe2x80x9c0xe2x80x9d bit.
The DRAM array 10 retrieves xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits from the memory cells 22 arranged along the complementary digit lines D0*, D1*, . . . , and Dn* in the same manner as described above.
DRAM arrays sometimes contain defective memory cells that are unable to reliably store xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits in the manner described above. In some instances, this occurs because the capacitance of the storage capacitors in these memory cells is too small, preventing the capacitors from retaining a sufficient electric charge to cause a change in voltage VSENSE on a digit line when discharged to the digit line that exceeds a sense amplifier""s detection threshold. In other instances, this occurs because the electric charge stored on the storage capacitors in these memory cells leaks away through a variety of mechanisms, also preventing the capacitors from retaining a sufficient electric charge to cause a detectable change in voltage VSENSE on a digit line when discharged to the digit line. In either case, because the change in voltage VSENSE caused by discharging the electric charges stored by the storage capacitors in these memory cells cannot be detected by a sense amplifier, the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits represented by the electric charges stored in these memory cells are unretrievable.
DRAM arrays are also sometimes unable to reliably store xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits in certain memory cells because the detection threshold of the cells""associated sense amplifier is too large for the sense amplifier to detect a change in voltage VSENSE caused by one of the cells discharging to the digit line. In this case as well, the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits represented by the electric charges stored in these cells are unretrievable.
Generally, when DRAM arrays are found to be defective in-this way, an attempt is made to repair the arrays by replacing defective memory cells and defective sense amplifiers in the arrays with redundant memory cells provided in redundant rows or columns in the arrays and with redundant sense amplifiers provided in the redundant columns.
Conventionally, when a redundant row is used to repair a DRAM array containing a defective memory cell, a row address that identifies the defective cell""s row is permanently stored in the array by blowing selected fuses or anti-fuses in the array. Then, during normal operation of the DRAM array, if the array receives a request to access a memory cell having a memory address including a row address portion that corresponds to the stored row address, redundant circuitry in the array directs the array to access a redundant memory cell in the redundant row instead of accessing the memory cell identified by the received memory address. Since every memory cell in the defective cell""s row has the same row address, every cell in the defective cell""s row, both operative and defective, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column is used to repair a DRAM array containing a defective memory cell, a column address that identifies the defective cell""s column is permanently stored in the array by blowing selected fuses or anti-fuses in the array. Then, during normal operation of the DRAM array, if the array receives a request to access a memory cell having a memory address including a column address portion that corresponds to the stored column address, redundant circuitry in the array directs the array to access a redundant memory cell in the redundant column instead of accessing the memory cell identified by the received memory address. Since every memory cell in the defective cell""s column has the same column address, every cell in the defective cell""s column, both operative and defective, is replaced by a redundant memory cell in the redundant column.
The process described above for repairing a DRAM array using redundant rows and columns is well known in the art, and is described in various forms in U.S. Pat. Nos. 4,459,685, 4,601,019, 5,422,850 and 5,528,539.
Because the conventional repair process described above uses an entire redundant row or column to repair each defective memory cell in a DRAM or other memory array, the number of defective memory cells that can be repaired in an array is limited by the number of redundant rows or columns in the array which, in turn, is limited by the space available in the array for redundant rows or columns. As a result, it is not uncommon for defective DRAM and other memory arrays to be discarded because the conventional repair process cannot repair the quantity of defective memory cells they contain. This problem is often exacerbated by the discovery of defective redundant memory cells in the available redundant rows or columns. Obviously, it would be preferable to be able to repair these defective arrays rather than discard them.
Therefore, there is a need in the art for an improved device and method for repairing DRAM arrays and other memory arrays. Such an improved device and method should be applicable to arrays containing memory cells that are unable to reliably store xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits because their storage capacitors do not retain a sufficient electric charge, or because their associated sense amplifiers have a detection threshold that is too large.
The present invention provides an apparatus for repairing a memory array, such as a DRAM array, that includes a pair of complementary digit lines through which memory cells activated by word lines selected in accordance with row addresses are accessed. The array may need repair, for example, when a memory cell in the array is unable to properly store xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d bits because the charge it retains representing a bit is not sufficient to cause a detectable change in voltage on one of the digit lines when discharged to the digit line.
When repair is needed, enabling circuitry (e.g., fuses or anti-fuses) in the apparatus enables repair of the array, and word line energizing circuitry (e.g., a row decoder) responsive to the enabling circuitry energizes more than one word line in the array in accordance with each row address so more than one memory cell is accessed through the digit lines for each row address. As a result, the apparatus stores a single xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d bit as a charge in multiple memory cells. Then, when the apparatus retrieves the single bit, the bit""s representative charges stored in the multiple memory cells are discharged to the digit lines to cause a change in voltage on the digit lines that is greater than, and therefore more likely to be detectable than, a change in voltage on the digit lines caused by discharging a representative charge stored in a single memory cell to the digit lines in the conventional manner.
In other embodiments of the present invention, a memory system, an integrated circuit die, and a semiconductor wafer include the repair apparatus and memory array described above. In another embodiment, an electronic system includes input, output, processor, and memory devices, and the memory device includes the repair apparatus and memory array described above.
In a further embodiment, the present invention provides an apparatus for repairing a memory array. The memory array is of the type in which stored bits are read by detecting a change in voltage between two conductors caused by sharing a charge stored in a memory cell in the array with one of the conductors. The apparatus repairs the array when some memory cells in the array cannot retain a sufficient charge to cause a detectable change in voltage on one of the conductors. The apparatus includes circuitry directing each memory cell in a group of cells in the array to store a charge representing a single stored bit and, when the single stored bit is being read, to share its stored charge with one of the conductors.
In a still further embodiment, the present invention provides an apparatus for repairing a memory array. The memory array is of the type in which stored bits are accessed by using sense amplifiers to detect a change in voltage between two conductors caused by sharing a charge stored in a memory cell in the array with one of the conductors. The apparatus repairs the array when some of the sense amplifiers in the array cannot detect a change in voltage on one of the conductors caused by sharing a charge stored in one of the memory cells with one of the conductors. The apparatus includes circuitry directing each memory cell in a group of cells in the array to store a charge representing a single stored bit and, when the single stored bit is being accessed, to share its stored charge with one of the conductors.
In an additional embodiment, a memory system includes a memory array including pairs of complementary digit lines, alternating even and odd word lines, and memory cells controlled by the word lines and accessed through the digit lines. Address buffers receive memory addresses and output corresponding row and column addresses, and row decoder circuitry energizes at least two word lines in accordance with each row address. A column decoder outputs a column select signal in accordance with each column address, and sense amplifier and input/output gating circuitry selects a pair of complementary digit lines in the array in accordance with each column select signal. As a result, two or more memory cells that are each controlled by one of the energized word lines are accessed through one of the selected digit lines. A data buffer provides communication between the accessed memory cells and external circuitry.
In a further embodiment, a memory system includes a memory array including pairs of complementary digit lines, word lines, and memory cells controlled by the word lines and accessed through the digit lines. Address buffers receive multiplexed memory addresses in the form of a first plurality of address bits followed in time by a second plurality of address bits. The address buffers also output a row address and a first portion of a column address corresponding to each memory address"" associated first plurality of address bits, and output a second portion of the column address corresponding to each memory address""associated second plurality of address bits. Row decoder circuitry energizes at least two word lines in accordance with each row address, and a column decoder outputs a column select signal in accordance with the first and second portions of each column address. Sense amplifier and input/output gating circuitry selects a pair of complementary digit lines in the array in accordance with each column select signal so at least two memory cells controlled by the energized word lines are accessed through one of the selected digit lines. As a result, the accessed memory cells together may store or output a single memory bit to external circuitry. A data buffer provides communication between the accessed memory cells and external circuitry.
In a still further embodiment, a memory system includes a memory array including pairs of complementary digit lines, word lines, and memory cells controlled by the word lines and accessed through the digit lines. Row address bit terminals receive a first plurality of address bits associated with a non-multiplexed memory address, and column address bit terminals receive a second plurality of address bits associated with the non-multiplexed memory address. Address buffers output a row address corresponding to a first portion of the first plurality of address bits and output a column address corresponding to both the second plurality of address bits and a second portion of the first plurality of address bits. Row decoder circuitry energizes at least two word lines in accordance with the row address, and a column decoder outputs a column select signal in accordance with the column address. Sense amplifier and input/output gating circuitry selects a pair of complementary digit lines in the array in accordance with the column select signal. As a result, at least two memory cells controlled by the energized word lines are accessed through one of the selected digit lines. A data buffer provides communication between the accessed memory cells and external circuitry.
In a still additional embodiment, a method for storing a bit in a memory array having a plurality of memory cells each coupled to one of a pair of complementary digit lines includes providing a charge representing the bit on each of the digit lines, storing the charge provided on one of the digit lines in at least one of the memory cells, and storing the charge provided on one of the digit lines in at least one other of the memory cells.
In another embodiment, a method of testing a repair for a memory array of the type to store a bit by storing a charge in a memory cell, and also of the type to access the bit by sharing the stored charge with one of two conductors and then detecting a resulting change in voltage between the conductors, comprises: directing the memory cells in a group of memory cells in the memory array to each store the same bit by each storing a charge representing the bit; directing each memory cell in the group of memory cells to share its stored charge with one of the conductors; and attempting to detect a change in voltage between the conductors resulting from the memory cells in the group sharing their stored charges with the conductors.